Patent
1996-05-20
1999-07-13
Sheikh, Ayaz R.
395739, G06F 946
Patent
active
059238879
ABSTRACT:
An improved programmable interrupt controller for use in a computer system including one or more interrupt service providers (ISPs), usually central processing units (CPUs). At least one CPU and a main memory system are coupled to a host bus. A bus bridge device couples the host bus to the expansion bus. At least one I/O device is coupled to the expansion bus and generates an interrupt request signal. The bus bridge and other bus devices may also generate interrupt request signals. A programmable interrupt controller receives the interrupt requests and provides processor interrupt signals as well as information regarding resource requirements necessary for servicing the interrupts to the one or more CPUs. The programmable interrupt controller also receives interrupt acknowledge signals from the one or more CPUs.
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Advanced Micro Devices , Inc.
Kivlin B. Noel
Sheikh Ayaz R.
Wiley David A.
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