Semiconductor memory device having three-transistor type memory

Details Semiconductor memory device having three-transistor type memory Semiconductor memory device having three-transistor type memory

1988-11-02

1990-06-19

Moffitt, James W.

Static information storage and retrieval

Systems using particular element

Semiconductive

365149, 365222, G11C 1140, G11C 1124, G11C 700

Patent

active

049358960

ABSTRACT:
A memory cell array (61) comprises a plurality of three-transistor type memory cells (10) arranged in a plurality of rows and columns. A plurality of pairs of write bit lines (WB1, WB2) and a plurality of read bit lines (RB) are provided corresponding to each column of the memory cell array (61). The plurality of write word lines (WWL) and the plurality of read word lines (RWL) are provided corresponding to each row of the memory cell array (61). Information is written to memory cells (10) in odd rows through the respective one write bit lines of the pairs of write bit lines (WB1, WB2), and information is written to memory cells (10) in even rows through the respective other write bit lines of the pairs of write bit lines (WB1, WB2). A sense amplifier (30) is connected to each of the pairs of write bit lines (WB1, WB2). At the time of write operation, refresh operation is performed by the sense amplifier (30) with respect to memory cells (10) in non-selected columns.

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