Semiconductor integrated circuit for processing image data

Details Semiconductor integrated circuit for processing image data Semiconductor integrated circuit for processing image data

1995-01-23

1997-09-30

Tung, Kee M.

Computer graphics processing and selective visual display system

Display driving control circuitry

Controlling the condition of display elements

395511, 345201, G06F 1576

Patent

active

056734220

ABSTRACT:
A frame buffer memory includes a main memory of a DRAM, a cache memory of a SRAM, a first transfer bus for transferring data of 256 bits, for example, between the main memory and the cache memory, a pixel processing unit for carrying out a predetermined operational process according to data provided from the cache memory and externally applied data, a compare unit for comparing the data provided from the cache memory with externally applied data, a transfer bus for transferring data from the cache memory to the pixel processing unit and the compare unit, a transfer bus for transferring resultant data from the pixel processing unit to the cache memory, and a serial access memory for storing data read out from the main memory and providing the stored data serially to an outside world. According to the structure, an .alpha.-blend process, a raster operation, a Z compare process and the like required for graphics can be carried out at high speed with flexibility.

REFERENCES:
patent: 4718091 (1988-01-01), Kobayashi et al.
patent: 5185856 (1993-02-01), Alcorn et al.
patent: 5465224 (1995-11-01), Guttag et al.
patent: 5517603 (1996-05-01), Kelley et al.
"Graphics Processing with the 88110 Risc Microprocessor", Julie Shipnes, IEEE 1992, pp. 169-174.

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