Semiconductor memory device having hierarchy control circuit arc

Static information storage and retrieval – Addressing – Including particular address buffer or latch circuit...

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Details

Other Related Categories

365 63, 36523003, G11C 800

Type

Patent

Status

active

Patent number

058944486

Description

ABSTRACT:
Memory mats provided in four regions formed by dividing a semiconductor chip are each further divided into a plurality of memory arrays along the longer side direction of the chip, row related circuits are provided between the memory arrays along the shorter side direction of the chip, and column decoders are provided along the longer side direction of the chip. An internal control signal from a master control circuit in the central part of the chip is transmitted in the central region with respect to the shorter side direction of the chip, buffer circuits are provided to an internal control signal transmission bus, and an internal signal is transmitted to the row related circuit and the column decoder by the buffer circuit. The length of the signal line to drive is shortened, and therefore the signal can be transmitted at a high speed, thus enabling high speed accessing. Thus, signal propagation delay can be reduced even if the chip size increases.

REFERENCES:
patent: 5422856 (1995-06-01), Sasaki et al.
patent: 5477488 (1995-12-01), Subramani
patent: 5493535 (1996-02-01), Cho
patent: 5497349 (1996-03-01), Nakai et al.
patent: 5627792 (1997-05-01), Tsujimoto
patent: 5629903 (1997-05-01), Agata

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