Circuits and methods for multi-level data through a single input

Details Circuits and methods for multi-level data through a single input Circuits and methods for multi-level data through a single input

1998-02-23

1999-04-20

Nelms, David

Static information storage and retrieval

Read/write circuit

Parallel read/write

36518903, 36518907, 36518909, 36518911, 365168, G11C 700

Patent

active

058963375

ABSTRACT:
A method and memory circuits for increasing the data bandwidth per microprocessor operation cycle is provided. The memory circuits provide the additional bandwidth without additional input/output (I/O) pins or requiring decreased cycle times. Multiple bits of data are passed through a single input/output pin with each operation cycle. The multiple bits of data are stored in or retrieved from multiple memory cells in each cycle. The I/O pins carry analog signals which represent multiple values of binary data. This method of compressing data can be applied to any device that would benefit from the ability to transfer more data through a limited number of I/O pins.

REFERENCES:
patent: 5302870 (1994-04-01), Chern
patent: 5367655 (1994-11-01), Grossman et al.
patent: 5371869 (1994-12-01), Lee
patent: 5394362 (1995-02-01), Banks
patent: 5457650 (1995-10-01), Sigiura et al.
patent: 5500825 (1996-03-01), Onaya et al.

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