Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1997-01-03
1999-04-20
Fahmy, Wael
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257353, 257 66, H01L 2701, H01L 2712, H01L 2976
Patent
active
058959572
ABSTRACT:
A process is disclosed for preparing a silicon-on-sapphire wafer suited for fabrication of fully depleted field effect transistors. A fully depleted field effect transistor (FET) which has minimum parasitic charge in the conduction channel and a process to make same are described. The device is made in and relies on the silicon layer on sapphire which has minimal charge intentionally introduced into the conduction channel. Both N-type and P-type transistors are described. Methods for defining threshold voltage are also described. Specific examples of the devices are presented including specific materials selections for threshold voltage options.
Manufacturing processes are described, including a preferred embodiment based on ultra thin silicon on sapphire. The devices can be fabricated using conventional silicon techniques; both silicided and non-silicided versions are presented.
Advantages include threshold voltages determined by fundamental material properties; high performance devices due to reduced carrier scattering, low transverse electric fields and elimination of the body effect; threshold voltages virtually independent of temperature; simplicity of modeling due to reduction or elimination of parasitic effects; device and process simplicity; ease of scaling and an option for inherently symmetric threshold voltages for N-channel and P-channel MOSFETs (i.e. .vertline.V.sub.tn .vertline.=.vertline.V.sub.tp .vertline.).
REFERENCES:
patent: 3562608 (1971-02-01), Gallagher et al.
patent: 3829881 (1974-08-01), Kohashi
patent: 4177084 (1979-12-01), Lau et al.
patent: 4198649 (1980-04-01), Berry
patent: 4385937 (1983-05-01), Ohmura
patent: 4418470 (1983-12-01), Naster et al.
patent: 4425700 (1984-01-01), Sasaki et al.
patent: 4463492 (1984-08-01), Maeguchi
patent: 4509990 (1985-04-01), Vasudev
patent: 4523963 (1985-06-01), Ohta et al.
patent: 4588447 (1986-05-01), Golecki
patent: 4607176 (1986-08-01), Burrows et al.
patent: 4615762 (1986-10-01), Jastrzebski et al.
patent: 4617066 (1986-10-01), Vasudev
patent: 4659392 (1987-04-01), Vasudev
patent: 4766482 (1988-08-01), Smeltzer et al.
patent: 4775641 (1988-10-01), Duffy et al.
patent: 4843448 (1989-06-01), Garcia et al.
patent: 5027171 (1991-06-01), Reedy et al.
patent: 5141882 (1992-08-01), Komori et al.
patent: 5229644 (1993-07-01), Wakai et al.
patent: 5294823 (1994-03-01), Eklund et al.
patent: 5300443 (1994-04-01), Shimabukuro et al.
Golecki et al., "Recrystallization of Silicon-on-Sapphire by CW Ar Laser Irradiation: Comparison Between the Solid and the Liquid-Phase Regimes"; Appl. Phys. Lett. 37(10), 1980, pp. 919-921.
Inoue et al. "Crystaline Disorder Reduction and Defect-Type Change in Silicon-on-Sapphire Films by Silicon Implantation and Subsequent Thermal Annealing"; Appl. Phys. Lett. 36(1), 1980, pp. 64-66.
Golecki et al., "Improvement of Crystalline Quality of Epitaxial Silicon-on-Sapphire by Ion-Implantation and Furnace Regrowth"; Solid State Electronics vol. 23, 1980, 803-806.
Linnros et al., "Ion-Beam Induced Epitaxial Regrowth of Amorphous Layers in Silicon on Sapphire"; Physical Review B, vol. 30, No. 7, 1984, pp. 3629-3638.
Lau et al., "Improvement of Crystalline Quality of Epitaxial Si Layers by Ion Implantation Techniques"; Appl. Phys. Lett. 34(1), 1979, pp. 76-78.
P.R. de la Houssaye, et al., "Fabrication of n-channel metal-oxide-semiconductor field-effect transistors with 0.2.mu.m gate lengths in 500 A thin film silicon on sapphire", Journal of Vacuum Science and Technology: Part B, vol. 10, No. 6, pp. 2954-2957, Nov./Dec. 1992.
P.H. Woerlee, et al., "Half-Micron CMOS on Ultra-Thin Silicon on Insulator", Technical Digest of the International Electron Devices Meeting 1989, Washington, D.C., pp. 821-824, Dec. 3-6, 1989.
Nobuo Sasaki et al., "A CMOS/SOS Synchronous Static RAM Fabricated with an Advanced SOS Technology", Japanese Journal of Applied Physics, Supplement 18-1, vol. 18, pp. 57-62, 1979.
Adele E. Schmitz et al., "A Deep-Submicrometer Microwave/Digital CMOS/SOS Technology", IEEE Electron Device Letters, vol. 12, No. 1, pp. 16-17, Jan. 1991.
Tsu-Jae King et al., A Low-Temperature "(.ltorsim.550.degree.C) Silicon-Germanium MOS Thin-Film Transistor Technology for Large-Area Electronics", Technical Digest of the International Electron Devices Meeting 1991, Washington, D.C., pp. 567-570, Dec. 8-11, 1991.
R.E. Reedy et al., "Characterization of Defect Reduction and Aluminum Redistribution in Silicon Implanted SOS Films", Journal of Crystal Growth, vol. 58, No. 1, pp. 53-60, Jun. 1982.
R.E. Reedy et al., "Suppressing A1 Outdiffusion in Implantation Amorphized and Recrystallized Silicon on Sapphire Films", Applied Physics Letters. vol. 42, No. 8, pp. 707-709, Apr. 1983.
G.A. Garcia et al., "High-Quality CMOS on Thin (100 nm) Silicon on Sappphire", IEEE Electron Device Letters, vol. 9, No. 1, pp. 32-34, Jan. 1988.
R.E. Reedy et al., "Thin (100 nm) SOS for Application to Beyond VLSI Microelectronics"Mat. Res. Soc. Symp. Proc., vol. 107, pp. 365-376, 1988.
Reedy et al.; "(100nm) SOS for application to beyond VLSI microelectronics"; MAt. Res. Soc. Proc., vol. 107, pp. 365-376.
Burgener Mark L.
Reedy Ronald E.
Epperson Dennis H.
Fahmy Wael
Peregrine Semiconductor Corporation
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