Semiconductor integrated circuit arrangement for preventing latc

Details Semiconductor integrated circuit arrangement for preventing latc Semiconductor integrated circuit arrangement for preventing latc

1991-07-15

1993-08-17

Hille, Rolf

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257379, 257392, 257394, H01L 2702, H01L 2968, H01L 2978

Patent

active

052371956

ABSTRACT:
A semiconductor integrated circuit arrangement prevents the occurrence of latch up. The circuit includes a first semiconductor island of a first conductivity type and a second semiconductor island of the first conductivity type located within a base semiconductor region of a second conductivity type. A resistive diffusion region of the second conductivity type is located within the first semiconductor island region. The second semiconductor region is connected to ground. A high potential electrode connected to the resistive diffusion region is also connected to the first semiconductor island region. In this manner, an emitter and a base of a parasitic transistor of the integrated circuit are connected together to prevent the parasitic transistor from operating in a conductive state, thereby preventing latch up.

REFERENCES:
patent: 3990092 (1976-11-01), Yoshimura
patent: 4161417 (1979-07-01), Yim et al.
patent: 4660067 (1987-04-01), Ebina
patent: 4740827 (1988-04-01), Niitsu et al.
patent: 4805008 (1989-02-01), Yao et al.
patent: 4862240 (1989-08-01), Watanabe et al.
patent: 4922317 (1990-05-01), Mihara
patent: 4952992 (1990-08-01), Blanchard
patent: 5142348 (1992-08-01), Imahashi et al.
patent: 5142641 (1992-08-01), Fujioka
G. J. Hadamard, "Integrated Circuits Having Reduced Parasitic Thyratron Effects", IBM Technical Disclosure Bulletin, vol. 14, No. 4, Sep. 1971, p. 1076.

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