Memory management system including an inclusion bit for maintain

Details Memory management system including an inclusion bit for maintain Memory management system including an inclusion bit for maintain

1991-10-16

1999-04-20

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711141, 711145, G06F 1212

Patent

active

058954899

ABSTRACT:
A memory management system for a computer, where cache coherency between a descriptor cache and data cache is preserved through an inclusion bit mechanism. In one embodiment, an inclusion bit is set for a descriptor cached in a data cache corresponding to a descriptor cached in a descriptor cache such that the association between the descriptors is indicated. Whenever a descriptor in the data cache with a set inclusion bit is altered, the entire descriptor cache is flushed by virtue of the set inclusion bit. Furthermore, in the same embodiment, a valid bit is set for a descriptor in the data cache which is cached from the descriptor table. Whenever a descriptor in the descriptor table, which has a valid bit set in the data cache, is modified, the valid bit is reset. And if the same descriptor with its valid bit reset has a set inclusion bit, then the entire descriptor cache is flushed. As a result, the cache coherency among descriptor cache, data cache and descriptor table is preserved in this improved memory management system.

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