Cache flushing methods and apparatus

Details Cache flushing methods and apparatus Cache flushing methods and apparatus

1997-02-24

1999-04-20

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711143, 711146, G06F 1200

Patent

active

058954880

ABSTRACT:
Methods and apparatus for managing a cache which includes a number of dirty lines in which (a) the percentage of dirty lines in the cache is determined, (b) the cache is flushed if the determined percentage of dirty lines exceeds a predetermined threshold, (c) whether a state of a system is idle is determined based on at least two indicators including (i) CPU idle percentage, (ii) data bus busyness percentage, (iii) percentage of dirty lines, and (iv) I/Os per second, and (d) if the state of the system is determined to be idle, a line of the cache is flushed.

REFERENCES:
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patent: 4775955 (1988-10-01), Liu
patent: 4827401 (1989-05-01), Hrustich et al.
patent: 5038278 (1991-08-01), Steely, Jr. et al.
patent: 5347634 (1994-09-01), Herrell et al.
patent: 5408644 (1995-04-01), Schneider et al.
patent: 5414827 (1995-05-01), Lin

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