Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-12-20
1999-04-20
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711119, 711133, 711141, 711145, G06F 1212
Patent
active
058954864
ABSTRACT:
A method and system for reducing bus traffic in a multiple processor system having a shared memory and processor related private caches. Store multiple word instructions are evaluated to determine whether a full cache line is to be modified. If the full cache line is to be stored, a cache line kill is issued on the system bus and the cache line is written to the cache. Any store operation of single word, or multiple words extending over portions of a cache line, invokes conventional memory coherence processes.
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Davis, Jr. Michael A.
International Business Machines - Corporation
Peikari J.
Salys Casimer K.
Swann Tod R.
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