Semiconductor memory device

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

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Details

36518911, 326108, G11C 800

Patent

active

061607525

ABSTRACT:
A semiconductor memory device comprising a plurality of row decoders, each having a precharge circuit connected to receive a precharge signal and a decode circuit connected to receive address signals. A level-shifted precharge signal is input to the precharge circuits.

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