Mask control device for LSI tester

Details Mask control device for LSI tester Mask control device for LSI tester

1996-06-21

1997-09-16

Beausoliel, Jr., Robert W.

Excavating

371 272, 39518201, G01R 3128

Patent

active

056688199

ABSTRACT:
A mask control device is disclosed comprising an address generator which generates a random pattern address, a serial pattern address, and a pattern mode signal. Random pattern memories store random pattern expected and mask waveform data to be used for a random pattern test. Serial pattern memories store serial pattern expected and mask waveform data to be used for a serial pattern test. First and second pin selectors arrange the serial pattern expected and mask waveform data to generate serial pattern expected and mask waveform data corresponding to tester pins and generate serial mode designating signals designating pins to which the serial pattern test is to be applied. A selector selects the random pattern expected waveform data or the serial pattern expected waveform data generated by the first pin selector based on the serial mode designating signals. A comparator compares output waveform data obtained from the device under test (DUT) with the waveform data from the selector. A logic operation circuit generates select signals based on the serial mode designating signal and the serial pattern mask waveform data from the second pin selector, and modulates the random pattern mask waveform data based on the select signal to generate mask waveform data. A mask control circuit carries out mask control using the mask waveform data generated by the logic operating circuit on the comparison result of the comparator.

REFERENCES:
patent: 4313200 (1982-01-01), Nishiura
patent: 4369511 (1983-01-01), Kimura et al.
patent: 4807229 (1989-02-01), Tada
patent: 4835774 (1989-05-01), Ooshima et al.
patent: 5170398 (1992-12-01), Fujieda et al.
patent: 5321641 (1994-06-01), Ohkubo
patent: 5432797 (1995-07-01), Takano
patent: 5481549 (1996-01-01), Tokuyama

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