Semiconductor die having rounded or tapered edges and corners

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Details

357 72, 357 55, H01L 2348

Patent

active

051191717

ABSTRACT:
An improved semiconductor die for plastic encapsulated semiconductor device packages which impedes the inherent delamination caused by the differing expansion coefficients of the semiconductor die and plastic encapsulation. Rounded or tapered die corners and die edges decrease the stress from the plastic encapsulation that acts upon the semiconductor die. This reduced stress slows the delamination progression and leaves the operational circuitry unaffected for an increased period of time thereby increasing device lifetime.

REFERENCES:
patent: 4675717 (1987-06-01), Herrero
Egawa et al., "A 1-Mbit Full Wafer MOS RAM", IEEE Trans. Electron Dev. vol. ED-27, No. 8, pp. 1612-1621.

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