Semiconductor memory device and access method for the same

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

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36523008, 365240, G11C 800

Patent

active

056687729

ABSTRACT:
A semiconductor memory device comprising a memory cell array includes a plurality of memory cells. The device includes: a predecoder for dividing a plurality of bits of an address signal into at least two bit strings so as to decode each bit string and output predecoded results of each bit string in parallel; a series of shift registers, each shift register being provided for a respective bit string, receiving the predecoded results of the corresponding bit string as shift data, shifting the received shift data, thereby generating and outputting predecoded signal bits; and a main decoder for decoding the predecoded signal bits output from the plurality of shift registers and selecting a memory cell in the memory cell array in accordance with the results of the decoding.

REFERENCES:
patent: 5369621 (1994-11-01), Mason
patent: 5495454 (1996-02-01), Fijkuzo
patent: 5528551 (1996-06-01), Pinkham
patent: 5579268 (1996-11-01), Seo et al.

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