Method for the self-aligned silicide formation in IC fabrication

Details Method for the self-aligned silicide formation in IC fabrication Method for the self-aligned silicide formation in IC fabrication

Filed on

1986-11-17

Date issued

1988-04-05

Examiner

Powell, William A.

Patent Class

Adhesive bonding and miscellaneous chemical manufacture

SubClass

Delaminating processes adapted for specified product

SubSubClass

Delaminating in preparation for post processing recycling step

Other Related Categories

156646, 156648, 156653, 156656, 156657, 1566591, 156662, 357 231, 357 41, 357 67, 437 41, 437200, 437228, H01L 21306, B44C 122, C03C 1500, C23F 102

Type

Patent

Status

active

Patent number

047356804

Description

ABSTRACT:
The invention discloses an improved process to form a silicide layer on an integrated circuit structure. The conventional lateral silicide growth is prevented by employing a slot configuration which is formed with the self-aligned process. It is simple to construct a multilevel interconnect scheme with the practice of the invention.

REFERENCES:
patent: 4521952 (1985-06-01), Riseman
patent: 4528744 (1985-07-01), Shibata
patent: 4577392 (1986-03-01), Peterson

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