Method of improving silicon-on-insulator uniformity

Details Method of improving silicon-on-insulator uniformity Method of improving silicon-on-insulator uniformity

1987-03-30

1988-04-05

Bashore, S. Leon

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156645, 156648, 156656, 156657, 156662, 51317, 437 62, 437233, 437245, 437249, 437966, 437974, H01L 2108, H01L 21302, B24B 100

Patent

active

047356790

ABSTRACT:
A method of improving silicon-on-insulator uniformity using polishing. A polishing stop layer of substantially uniform thickness is provided having a first side which is made coplanar with a first side of a thicker layer of semiconductor material. A polishing process is applied to a second side of the semiconductor material until a second side of the polishing stop layer is encountered, such that the substantially uniform thickness of the polishing stop layer can be used to define the semiconductor material to a layer of uniform thickness.

REFERENCES:
patent: 3009841 (1961-11-01), Faust
patent: 3386864 (1968-06-01), Silvestri et al.
patent: 3740280 (1973-06-01), Ronen
patent: 3911562 (1975-10-01), Youmans
patent: 3979237 (1976-09-01), Marcom et al.
patent: 4037306 (1977-07-01), Gutteridge et al.
patent: 4057939 (1977-11-01), Basi
patent: 4233091 (1980-11-01), Kawabe
patent: 4571819 (1986-02-01), Rogers et al.
patent: 4596071 (1986-06-01), Kita
patent: 4601779 (1986-07-01), Abernathey et al.
F. E. Goetz and J. R. Hause, "Planetary `Free` Wafer Polisher", IBM Technical Disclosure Bulletin, vol. 15, No. 6, dated Nov. 1972.
R. R. Shaw, R. R. Tummala, "Photosensitive Glass for Producing Recessed Metallurgy, Eliminating Need for Planarization", IBM Technical Disclosure Bulletin, vol. 26, No. 3A, dated Aug. 1983, p. 1094.
J. R. Kitcher, "Reactive Etch Process for Metal Wiring Using a Buried Mask", IBM Technical Disclosure Bulletin, vol. 23, No. 4, dated Sep. 1980, p. 1394.
C. H. Scrivner, "Polishing Technique to Remove Aluminum Lands from Semiconductor Chips", IBM Technical Disclosure Bulletin, vol. 24, No. 4, Sep. 1981.
C. H. Scrivner, "Test Site Failure Analysis: Two Levels of Metal for Isolation of Components", IBM Technical Disclosure Bulletin, vol. 20, No. 11A, Apr. 1978.
W. K. Chu, P. J. Tsang, R. C. Joy, "Process for Producing Dielectrically Isolated Single Crystal Silicon", IBM Technical Disclosure Bulletin, vol. 24, No. 9, Feb. 1982, pp. 4734-4735.
V. J. Silvestri, "Silicon on Insulator Processes for FET and Bipolar Device", IBM Technical Disclosure Bulletin, vol. 27, No. 8, Jan. 1985, pp. 4599-4604.
J. B. Laskey, "Wafer Bonding for Silicon on Insulator Technologies", Appl. Phys. Lett., 48(1), Jan. 6, 1986; pp. 78-80.
J. B. Laskey, S. R. Stiffer, F. R. White, J. R. Abernathey, "Silicon on Insulator (SOI) by Bonding and Etch-Back", IEDM 28.4, Dec. 1-4, 1985.
Copending U.S. Applications: Ser. No. 791,860, Beyer et al, "Chem-Mech Polishing Method for Producing Coplanar Metal/Insulator Films on Substrate", filed 10/28/85.
Copending U.S. Applications: Ser. No. 791,861, Beyer et al, "Method for Removing Protuberances at the Surface of a Semiconductor Wafer Using a Chem-Mech Polishing Technique", filed Oct. 28, 1985 and Ser. No. 791,887, Chow et al, "Method for Producing Coplanar Multi-Level/Insulator Films on a Substrate and for Forming Patterned Conductive Lines Simultaneously with Stud Vias", filed Oct. 28, 1985.

Affiliated with

Also associated with

Rating

Method of improving silicon-on-insulator uniformity does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of improving silicon-on-insulator uniformity, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of improving silicon-on-insulator uniformity will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2231840