Method of making FET with two reverse biased junctions in drain

Details Method of making FET with two reverse biased junctions in drain Method of making FET with two reverse biased junctions in drain

1995-08-22

1996-06-18

Fourson, George

Fishing, trapping, and vermin destroying

437 41, 437 44, H01L 218234

Patent

active

055277217

ABSTRACT:
A polysilicon gate (42) of an N-channel MOSFET (40) includes a P+ doped central portion (42a), and N+ doped lateral portions (42b,42c) which face an N-type source (24c) and drain (26c) respectively. An N-type dopant is implanted into the surface portion of a P-type channel region (18) to reduce the surface doping and adjust the transistor threshold voltage to approximately 0.8 volts. The lowered channel doping reduces the electric field at the drain (26c) and suppresses injection of hot electrons from the drain (26c) into the gate oxide (14), and also reduces the electric field across the gate oxide (14) and suppresses charging thereof by hot electrons. N-type and P-type graded strata (26a,26b) are formed between the drain (26c) and substrate (12) and create two reverse biased diode junctions which block flow of drain current from the channel region (18), thereby eliminating the creation of hot electrons and impact ionization in the bulk portion of the drain diode, and channel charge carriers through the surface portion of the channel region (18). The surface portions of the channel region (18), drain (26c) and graded strata (26a,26b) are shorted together to form a shorting surface channel through which the charge carriers are constrained to flow.

REFERENCES:
patent: 3855610 (1974-12-01), Masuda et al.
patent: 4714519 (1987-12-01), Pfiester
patent: 4746624 (1988-05-01), Cham et al.
patent: 4931408 (1990-06-01), Hshieh
patent: 4943537 (1990-07-01), Harrington III
patent: 5124770 (1992-06-01), Umemoto et al.

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