Electrical computers and digital processing systems: memory – Address formation – Address mapping
Patent
1996-07-01
2000-06-06
Gossage, Glenn
Electrical computers and digital processing systems: memory
Address formation
Address mapping
711209, 711219, 711133, 711207, G06F 1210
Patent
active
060732245
ABSTRACT:
A circuit and method for segregating address entries of memory, internal to an address translation unit, into locked and unlocked regions. The locked region is a portion of the memory that can be invalidated by a lesser number of events than the unlocked region. In one embodiment, replacement circuitry of the address translation unit may invalidate address translations only stored in the unlocked region. The replacement circuitry comprises a counter to produce a first count value upon detecting that at least a first command has been issued to the address translation unit and each entry of the memory is currently in a valid state. Also, the replacement circuitry comprises an increment controller to control the counter to produce the first count value that addresses an entry of the memory within the second address range.
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patent: 5592625 (1997-01-01), Sandberg
patent: 5708790 (1998-01-01), White et al.
K. Holden and S. McMahan, "Integrated Memory Management for the MC68030," 1987 IEEE International Conference on Computer Design, Oct. 5, 1987, pp. 586-589.
Gossage Glenn
Sun Microsystems Inc.
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