System for peer-to-peer mastering over a computer bus

Details System for peer-to-peer mastering over a computer bus System for peer-to-peer mastering over a computer bus

1998-03-31

2000-06-06

Ray, Gopal C.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710101, 710128, 370402, G06F 1300, G06F 1342

Patent

active

060731982

ABSTRACT:
A system for communicating information between requester and target devices in a computer having a multiple bus architecture. The system supports deferred transactions of cache line read requests over a host bus, e.g., the Pentium II or Pentium Pro (P6) bus. The system employs a host bridge to issue deferred transactions over the P6 bus without interrupting or involving the main processor. The system comprises a first device, electrically connected to the requester, which receives a request from the requester. The system further comprises a second device, electrically connected to the first device, which transmits the request with a defer enable signal over the P6 bus. The system further comprises a third device, electrically connected to the P6 bus, which communicates the request having a defer enable signal to the target.

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