System and method for controlling main memory employing pipeline

Details System and method for controlling main memory employing pipeline System and method for controlling main memory employing pipeline

1998-10-30

2000-09-05

Ray, Gopal C.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710113, 710119, 710240, 711 5, 711104, G06F 1316, G06F 13362, G06F 13368

Patent

active

061157686

ABSTRACT:
A memory control system comprises a main memory including a plurality of banks; two or more requesters each of which includes an MPU or an I/O section which outputs a request that is addressed to a bank of the main memory; and a pipeline-controlled system bus connecting the main memory and each requester. Each requester includes a request sending control circuit, a system bus arbitration circuit, and a bank busy management section. The request sending control circuit which received a request from the MPU or the I/O section executes a system bus acquisition request to the system bus arbitration circuit of the requester and other requesters after confirming that the bank to which the request has been addressed is not busy for the request by referring to the bank busy management section. The system bus arbitration circuit executes distributed arbitration between system bus acquisition requests and informs the bank busy management section about a request type and a bank number concerning a system bus acquisition request that could acquire the system bus. Based on the information, the bank busy management section manages bank busy statuses of the banks with regard to each request type. The request sending control circuit sends the request to the main memory via the pipeline-controlled system bus if the system bus could be acquired in the distributed arbitration.

REFERENCES:
patent: 5412788 (1995-05-01), Collins et al.
patent: 5440713 (1995-08-01), Lin et al.
patent: 5548793 (1996-08-01), Sprague et al.
patent: 6026464 (2000-02-01), Cohen

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