Method for forming a highly planarized interlevel dielectric str

Details Method for forming a highly planarized interlevel dielectric str Method for forming a highly planarized interlevel dielectric str

1997-07-07

1999-04-13

Everhart, Caridad

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438788, 438695, 438787, H01L 21443

Patent

active

058937501

ABSTRACT:
A method is provided for forming a highly planarized interlevel dielectric layer over interconnects formed upon a frontside surface of an upper topography of a silicon wafer. An anisotropic silicon dioxide (oxide) layer is first deposited over the interconnects. Unlike conformal dielectric layers, anisotropic dielectric layers are able to fill narrow spaces between closely-spaced interconnects without creating voids in the process. The anisotropic oxide layer may be formed using a PECVD technique with the introduction of TEOS, O.sub.2, and He or NH.sub.3, or using an electron-cyclotron-resonance (ECR) plasma CVD method. A spin-on glass (SOG) layer is then formed over the anisotropic oxide layer. The liquid SOG material flows over the upper surface, filling narrow spaces without creating voids and producing a surface smoothing effect at isolated vertical edges. After curing of the SOG layer, a chemical-mechanical polishing (CMP) process is applied to the frontside surface. The CMP process increases the planarity of the frontside surface by reducing surface heights of elevated features more so than surface heights in recessed areas. After the silicon wafer is cleaned to remove CMP residue, an isotropic oxide layer may be deposited over the frontside surface to encapsulate the SOG layer.

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