Timing consistent dynamic compare with force miss circuit

Details Timing consistent dynamic compare with force miss circuit Timing consistent dynamic compare with force miss circuit

1996-05-01

1998-06-09

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711150, 711151, 711139, 711167, 711168, G06F 928, G06F 926

Patent

active

057651949

ABSTRACT:
A dynamic tag match circuit (10) has exclusive-OR gates (18) each of which receives one bit of an address signal (A) from cache tag RAM, an inverted bit of the address signal (NA) from the cache tag RAM, and one bit of an address signal (B) from an address translator. The exclusive-OR gates (18) are in parallel to each other and output a hit signal which is low only when a match occurs between the two address signals. Additionally, the hit signal is low only when the results of a force miss circuit (14) indicate that a force miss should not occur. The dynamic tag match circuit (10) further has a pull-up circuit (16) for precharging the output of the circuit (16) and for holding the output of the circuit (16) at one of the two logical levels. The force miss circuit (14) advantageously incorporates logic which coordinates the timing of the force miss evaluation with the arrival of the address (A) from the cache tag RAM. As a result, the timing of the circuit (10) is consistent regardless of where a miss originates, whether it be from the address compare circuit (12) or the force miss circuit (14). The consistency in timing simplifies the evaluation and characterization of any chip or circuit incorporating the dynamic compare circuit (10), increases the overall speed of the circuit (10), and simplifies the design of the circuits generating the force miss input signals as well as circuits downstream of the tag match circuit (10).

REFERENCES:
patent: 4357656 (1982-11-01), Saltz et al.
patent: 5237671 (1993-08-01), Freitas et al.
patent: 5325507 (1994-06-01), Freitas et al.
patent: 5553264 (1996-09-01), Ozveren et al.
patent: 5636363 (1997-06-01), Bourekas et al.

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