Timing circuit utilizing a clock tree as a delay device

Details Timing circuit utilizing a clock tree as a delay device Timing circuit utilizing a clock tree as a delay device

1998-06-03

2000-09-05

Santamauro, Jon

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

326 93, 326101, 327293, 327295, G03B 1318

Patent

active

061148776

ABSTRACT:
A timing circuit that utilizes the delay inherent in a clock tree to achieve a desired timing relationship between control or clock signals. The timing circuit is particularly applicable to high speed environments and to asynchronous logic, though it is also applicable to lower speed environments and synchronous logic. A method producing the desired control or clock signals is also disclosed.

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