Non-volatile semiconductor memory device in which data can be er

Details Non-volatile semiconductor memory device in which data can be er Non-volatile semiconductor memory device in which data can be er

1992-09-23

1994-08-09

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Erase

365185, 365900, G11C 700

Patent

active

053372816

ABSTRACT:
In a flash EEPROM having source lines separately provided for memory cell array blocks, a Y decoder and a transfer control circuit are controlled in response to data supplied as a command indicating an erase mode so that a predetermined potential may only be supplied to a source line latch circuit provided corresponding to any one of the memory cell array blocks through a bit line in the one memory cell array block in the erase mode. Each source line latch circuit, in response to the predetermined potential, latches data instructing to supply a high potential to a source line in a corresponding memory cell array block. Accordingly, stored data in memory cell array can be erased on a block basis without increasing the number of interconnections and the circuit scale.

REFERENCES:
patent: 5065364 (1991-11-01), Atwood
patent: 5095461 (1992-03-01), Miyakawa
Kynett et al., IEEE International Solid-State Circuits Conference, 1989 no month.

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