Method and apparatus for reducing cumulative time delay in synch

Details Method and apparatus for reducing cumulative time delay in synch Method and apparatus for reducing cumulative time delay in synch

1997-06-18

1998-06-09

Sheikh, Ayaz R.

395559, 395306, 395308, G06F 112

Patent

active

057649669

ABSTRACT:
An interface between first and second data buses includes a first bus state machine which controls data transfers from the first data bus to a data buffer. The interface includes a second bus state machine which controls data transfers from the data buffer to the second data bus. The data buffer includes a plurality of storage locations accessed on a first-in/first-out basis. A respective valid data flag for each storage location is set by the first bus state machine when data are stored in the storage location from the first data bus and is cleared by the second bus state machine when data are transferred from the storage location to the second data bus. The data valid flags are synchronized with first and second bus clocks respectively associated with the first and second bus state machines to assure that the data valid flags change synchronously with respect to each state machine. In order to reduce the time required to output sequential data from multiple data locations in the data buffer, each data valid flag is synchronized independently so that when the second bus state machine selects a new buffer location from which to output data, the data valid flag associated with the new buffer location is already synchronized with the second bus clock and can be immediately checked by the second bus state machine to determine if the data in the new buffer location is valid.

REFERENCES:
patent: 5274763 (1993-12-01), Banks
patent: 5535341 (1996-07-01), Shah et al.

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