Selective electroplating of copper for damascene process

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

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Details

438654, 438672, 205123, 205222, H01L 2144, C25D 502, C25D 552

Patent

active

060718145

ABSTRACT:
A method of removing a seed layer 30 from areas over an insulting layer 20 where metal lines and pads will not be formed so that electroplated metal 50 can be chemical-mechanical polished without metal residue problems 151 and dishing problems. A key step of the invention is the patterning of the seed layer 30 to remove areas 40 of seed layer 30 that are not near the trenches 24. The method is as follows. An insulating layer 20 is formed having a plurality of trenches 24. A seed layer 30 is formed over the insulating layer 24. The seed layer 30 is comprised of a trench seed layer 30B and a top seed layer 30A on the top surface of the first insulating layer. We pattern the top seed layer 30A by removing selected portions of the top seed layer 30A to form a seed layer "lip" 30C around the trenches 24 so that the remaining seed layer 30B 30C electrically connects the trench seed layers 30B in the plurality of trenches 24. Metal is plated on the trench seed layer 30B filling the trenches 24. Next, the metal 50 and the seed layer lip 30C are chemical-mechanical polished to remove the seed layer lip 30C and form a metal line pattern 50 filling the trenches 24.

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patent: 5933758 (1999-08-01), Jain
Dubin et al. "Selective Electroless Ni Deposition on a TiW Underlayer for Integrated Circuit Fabrication" Thin Solid Films. 226(1993) p87-93.
Chang et al. ULSI Technology, The McGraw-Hill Companies, Inc. 1997. p444-445.

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