Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1996-05-14
1998-06-09
Ngo, Ngan V.
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257372, 257395, 257655, H01L 2976, H01L 2994, H01L 31062, H01L 31113
Patent
active
057639213
ABSTRACT:
An n well and a p well are formed in a silicon substrate. The n well has n type impurity concentration peaks and a p type impurity concentration peak. The p well has p type concentration peaks. The impurity concentration peaks serving as channel stopper regions for isolating elements exist only in proximity to the lower surface of an isolation oxide film but not in element regions.
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Worderman et al, "A Buried N-Grid for Protection Against Radiation Induced Charge Collection in Electronic Circuits", IEDM. 1981, pp. 40-43.
Hayden et al, "A High-Performance Half-Micrometer CMOS Technology for Fast SRAM's ", IEEE Transactions on Electron Devices, vol. 38, No. 4 (Apr. 1991), pp. 876-885.
A 0.5 .mu.m Isolation Technology Using Advanced Poly Silicon Pad LOCOS (Appl), by Toshiyuki Nishihara et al, IEDM, pp. 100-103, 1988, no month.
Arima Hideaki
Okumura Yoshinori
Takeuchi Masahiko
Mitsubishi Denki & Kabushiki Kaisha
Ngo Ngan V.
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