Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1996-07-08
1998-06-09
Crane, Sara W.
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257363, 257389, 257401, H01L 2362
Patent
active
057639191
ABSTRACT:
A MOS transistor array structure for an electro-static discharge protection circuit in a semiconductor integrated circuit device, having dispersed parallel discharge paths. The MOS transistor array includes an n-well formed in a silicon substrate of the fabricated semiconductor device. A first dispersed drain region is formed in the n-well, and a source region is formed in the silicon substrate. A second dispersed drain region is formed in both the silicon substrate and the n-well. A gate of the transistor array is formed on the silicon substrate, and a first field oxide region is distributed at least partially in the dispersed drain region, so as to improve the even distribution of electric current in the event of an electro-static discharge. The transistor structure is compatible with a silicided process of device fabrication for fast device operation. Fabrication of the structure does not require additional procedural steps for achieving this compatibility.
REFERENCES:
patent: 5248892 (1993-09-01), Van Roozendaal et al.
patent: 5270565 (1993-12-01), Lee et al.
Gadi Krieger et al., "Nonuniform BSD Current Distribution Due to Improper Metal Routing", 1991 EOS/ESD Symposium Proceedings, Pgs. 104-109.
David Krakauer et al., "ESD Protection in a 3.3 V Sub-micron Silicided CMOS Technology", 1992 EOS/ESD Symposium Proceedings, pgs. 250-257.
Crane Sara W.
Winbond Electronics Corporation
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