Memory with redundancy and predecoded signals

Details Memory with redundancy and predecoded signals Memory with redundancy and predecoded signals

1986-12-22

1988-12-13

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Bad bit

365189, 365210, G11C 1140

Patent

active

047916150

ABSTRACT:
A memory has an address buffer which receives a row address and a column address and outputs these buffered address signals to a predecoder. A row decoder and column decoder use predecoded signals provided by the predecoder to select a row and a column from a main array. A redundant row is provided to replace a defective row from the main array. A programmable redundant decoder is programmable to select the redundant row in response to the predecoder signals which select the defective row.

REFERENCES:
patent: 4701884 (1987-10-01), Aoki et al.
patent: 4720817 (1988-01-01), Childers

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