Soft programmable logic array

Details Soft programmable logic array Soft programmable logic array

1986-11-21

1988-12-13

Heckler, Thomas M.

Boots, shoes, and leggings

364716, 307465, H03K 1900, G06F 738

Patent

active

047916028

ABSTRACT:
A programmable logic array is constructed of independently controllable logic building blocks of two types and special output logic to perform desired logic functions. The first building block is a functional element which is capable of performing any logical function of its input data to create output data. The functional elements shown are based on three inputs with a single output. The second basic type of building block is a pass-through/hold device which may either pass its input directly through as an output, or which may latch and hold the input until clocked. A plurality of logic levels or ranks of elements of the first type and ranks of the second type are interconnected so that the output can be various functions of the inputs. The logic array described here has first and second logic levels consisting of functional elements followed by a third level of pass-through/hold devices. The fourth and fifth logic levels are functional elements and pass-through/hold devices. The seventh and eighth logic levels are represented by another level of functional elements and pass-through/hold devices. Finally, the output logic is a plurality of output enable gates connected to tri-state buffers. The tri-state buffers may be high, low or floating. The output enable gate functions to either cause a direct pass-through of the input logic signal or activates the tri-state buffer to operate on the output logic level. The logic array is configured and controlled by input control bits to characterize the operation of each functional element and pass-through/hold device so that it functions either to produce combinations of input logic levels or to achieve particular logic states or a combination of the two functional modes. The output enable gates are controlled like the functional elements to either enable or disable tri-state control of the output buffers.

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