Memory cell array divided type multi-port semiconductor memory d

Static information storage and retrieval – Read/write circuit – Simultaneous operations

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36518901, 36523005, G11C 1300

Patent

active

052491650

ABSTRACT:
A memory cell array divided type multi-port memory device having random access circuit and serial access circuit, including: a plurality of cell array sections each having a plurality of memory cells disposed in a matrix form, the plurality of cell array sections being disposed in a column direction at a predetermined pitch, each the cell array section having a plurality of word lines and bit lines, the word lines being connected to the memory cells disposed in a row direction for selection of the connected memory cells, and the bit lines being connected to the memory cells disposed in a column direction for data transfer to and from the selected memory cells; a row decoder for activating a desired one of the word lines; sense amplifier provided for each the bit line for sensing data read out to each the bit line; a RAM port connected to the bit lines via RAM transfer gates; a column decoder for selectively turn on/off the RAM transfer gates; a plurality of data transfer lines each having a data transfer gate at the intermediate position thereof, the data transfer lines being connected to the bit lines and formed on a layer different from layers of the word lines and bit lines; data transfer gate control means for turning on/off a desired one of the data transfer gates; a plurality of serial resisters connected to the data transfer lines; a serial port connected via each serial transfer gate to each the serial register; and a serial decoder for serially turning on/off the serial transfer gates.

REFERENCES:
patent: 4569036 (1986-02-01), Fujii et al.
patent: 4937788 (1990-06-01), Harada
patent: 5177706 (1993-01-01), Shinohara

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