One-transistor one-capacitor memory cell structure for DRAMs

Details One-transistor one-capacitor memory cell structure for DRAMs One-transistor one-capacitor memory cell structure for DRAMs

1993-11-23

1995-08-15

Limanek, Robert P.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257305, 257347, H01L 2968

Patent

active

054422116

ABSTRACT:
A one-transistor one-capacitor memory cell structure is formed using the following steps. In a first step, a buried insulating film layer is formed in a semiconductor substrate and a semiconductor thin film layer is formed on the buried insulating film layer. In a second step, a capacitor trench is formed in the semiconductor substrate by penetrating through the buried layer and a dielectric film layer is formed on an inner side wall surface of the trench. Then, a conductive material is filled into the trench to form a capacitor. Finally, a MIS transistor is formed in the semiconductor thin film layer adjacent to the trench capacitor such that either the drain or the source makes contact with the conductive material.

REFERENCES:
patent: 4953125 (1990-08-01), Okumura et al.
patent: 5119155 (1992-06-01), Hieda et al.
patent: 5170372 (1992-12-01), Wong
M. Sakamoto et al, "Buried Storage Electrode (BSE) Cell for Megabit Drams", IEDM 85, 1985, IEEE at pp. 710-713.

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