Method and apparatus for preventing over-erasure of flash EEPROM

Details Method and apparatus for preventing over-erasure of flash EEPROM Method and apparatus for preventing over-erasure of flash EEPROM

1994-06-28

1996-02-06

Popek, Joseph A.

Static information storage and retrieval

Floating gate

Particular connection

365201, 36518533, G11C 1134

Patent

active

054901090

ABSTRACT:
An arrangement for controlling the application of erase biasing voltages to the memory devices of a flash EEPROM memory array which arrangement precludes application of any erase biasing voltage until all of the devices are tested to determine which if any devices are programmed, and then allows application of erase bias voltages only to those blocks of the memory array which include devices which are programmed. In one embodiment, a power-on state machine which is used to read the state of the devices to initialize the array is used to test the condition of the array whenever an erase is desired and latching means are used with each block to preclude any erasing until it is determined that the block, in fact, includes programmed devices.

REFERENCES:
patent: 5237535 (1993-08-01), Mielke et al.
patent: 5327383 (1994-07-01), Merchant et al.
patent: 5335198 (1994-08-01), Van Buskirk et al.
patent: 5359558 (1994-10-01), Chang et al.

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