SRAM cell and structure with polycrystalline p-channel load devi

Details SRAM cell and structure with polycrystalline p-channel load devi SRAM cell and structure with polycrystalline p-channel load devi

1992-07-27

1994-08-09

Limanek, Robert

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257393, 257755, 257382, 257903, H01L 2978

Patent

active

053369165

ABSTRACT:
An integrated circuit structure is suitable for use with SRAM memory devices. P-channel load devices are used in a 6-transistor SRAM cell. The P-channel devices are formed as polycrystalline silicon field effect transistors above the N-channel field effect transistors, which are formed in the substrate. In order to avoid formation of a P-N junction, a barrier layer is formed between P-type and N-type source/drain regions. The preferred barrier is a bilayer formed from a conductive material such as silicide over a doped polycrystalline silicon layer.

REFERENCES:
patent: 4569122 (1986-02-01), Chan
patent: 4581623 (1986-04-01), Wang
patent: 4814841 (1989-03-01), Masuoka et al.
patent: 5028975 (1991-07-01), Nagasawa et al.
patent: 5132771 (1992-07-01), Yamanaka et al.
patent: 5151387 (1992-09-01), Brady et al.

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