Semiconductor integrated circuit device having double well struc

Details Semiconductor integrated circuit device having double well struc Semiconductor integrated circuit device having double well struc

1994-10-04

1996-02-06

Loke, Steven H.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257371, 257402, 257345, H01L 2976, H01L 2994, H01L 31062

Patent

active

054897955

ABSTRACT:
A semiconductor device has a first P type well region (11) formed on an N type semiconductor substrate (10) and a second N type well region (12) formed so as to enclose the first well region. A third N type well region (13) formed on the semiconductor substrate is enclosed by a fourth P type well region (14). The first well region adjoins and is electrically connected to the fourth well region. Contact regions (15, 16) are formed on the first and third well regions to apply a bias voltage to the PN junction between the first and third well regions. An NMOS FET is formed in the first well region and a PMOS FET is formed in the third well region. The drain currents of the NMOS FET and PMOS FET are controlled by changing the reverse bias voltage applied to the two contact regions (15, 16). The depth of the first well region (11) is such that a depletion layer extending below the NMOS FET gate electrode (50) can be connected to a depletion layer formed at an interface between the first and second well regions. The depth of the third well region is such that a depletion layer extending below the gate electrode (5) of the PMOS FET can be connected to a depletion layer formed at the interface between the third and fourth well regions.

REFERENCES:
European Search Report, Jul. 7, 1994.
"1991 Symposium on VLSI Technology", Digest of Technical Papers, IEEE Cat. No. 91 ch 3017-1, May 28-30, 1991/OISO.
"Simultaneous Definition and Implant of N-Well and P-Channel Source/Drain", IBM Technical Disclosure Bulletin, vol. 29, No. 10, Mar. 1987.
Mizuno, Tomohisa, et al., "High Performance Shallow Junction Well Transistor (SJET)", Technical Digest of the Symposium of VLSI Technology (1992), pp. 109-110.
Yoshimura, Hisao, et al., "New CMOS Shallow Junction Well FET Structure (CMOS-SJET) for Low Power-Supply Voltage", IEDM Technical Digest (1992), pp. 909-912.

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