Static-random-access memory cell

Details Static-random-access memory cell Static-random-access memory cell

1995-01-30

1996-02-06

Hille, Rolf

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257351, 257369, 257393, 257903, H01L 2976

Patent

active

054897904

ABSTRACT:
An SRAM cell includes a pair of cross-coupled inverters where each inverter includes vertical n-channel and p-channel transistors having a gate electrode that is shared between the transistors that make up each inverter. The gate electrodes for the inverters laterally surround the channel regions of the p-channel load transistors to achieve a relatively high beta ratio without occupying a large amount of substrate surface area. Also, the gate electrodes increase the amount of capacitance of the storage nodes and decreases the soft error rate. The active regions of the latch transistors are electrically isolated from the substrate by a buried oxide layer, thereby decreasing the chances of latch-up.

REFERENCES:
patent: 4987090 (1991-01-01), Hsu et al.
patent: 5082795 (1992-01-01), Temple
patent: 5256588 (1993-10-01), Witek et al.
patent: 5285093 (1994-02-01), Lage et al.
patent: 5364810 (1994-11-01), Kosa et al.
Wolf; Silicon Processing For The VLSI Era; vol. 2; pp. 72-75 (1990).
Eklund, et al.; "A 0.5 .mu.m BiCMOS Technology for Logic and 4Mbit-class SRAM's;" IEDM; pp. 425-428 (1989).

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