Boots – shoes – and leggings
Patent
1986-03-27
1989-01-03
Shaw, Gareth D.
Boots, shoes, and leggings
364200, G06F 1340, G06F 300
Patent
active
047962216
ABSTRACT:
A memory control device which is able to interface with any memory regardless of the address information format for reading out data stored therein. The memory control device includes an address generator for generating address information for reading out corresponding data from the memory device, a data processing circuit such as a microprocessor for processing the stored data, a first bus for transmitting the stored data from the memory device to the data processing circuit, a second bus for transmitting address information generated by the address generator to the memory device, a third bus for selectively transmitting either the stored data to the data processing circuit or transmitting address data to the memory device, a mode signal generator for generating a mode signal, and a control circuit connected between the mode signal generator and the third bus for controlling the selective data transmission of the third bus in response to the mode signal.
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Intel "The 8086 Family User's Manual,", pp. A-3-A-184 Oct. 1979.
Eakman Christina M.
Kabushiki Kaisha Toshiba
Shaw Gareth D.
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