Electronic digital logic circuitry – Function of and – or – nand – nor – or not
Patent
1993-03-04
1994-12-06
Hudspeth, David R.
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
395 27, 326 35, G06F 1518
Patent
active
053714130
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
Neural networks are becoming increasingly important in many areas of adaptive signal processing and pattern recognition (D. E. Rumelhart, J. L. McClelland, Parallel Distributed Processing, Vols. I and II, MIT Press, Cambridge, Mass., 1986). There are different types of neural networks adapted to different tasks. Purely forward-coupled ADALINE-type neural networks are preferably used in pattern recognition (B. Widrow, R. G. Winter, R. A. Baxter, "Layered neural nets for pattern recognition", IEEE Trans. on ASSP, Vol. ASSP-36, No. 7, pp. 1109-1118, 1988).
The basic element of the ADALINE network is the "adaptive linear neuron" (ADALINE). This is understood to be a linear combiner followed by a sign decision means. The linear combiner generates a weighted sum from N input signals whose sign is determined by the sign decision means (single-stage quantizer) and is output as the output signal of the ADALINE (P. Strobach, "A neural network with Boolean Output Layer", Proc. IEEE Int. Conf. on ASSP, Albuquerque, N. Mex., April 1990).
By connecting such ADALINE neurons in series, ADALINE networks are obtained which--depending on the values of the weighting factors of the linear combiners --assign binary output signals to the signals applied to the free input nodes of the network.
These binary output signals are interpreted as a classification of the input signals. The input signals may be taken here from binary values, discrete multi-valued values, or an interval of continuous values. In order to be able to set a desired classification of the input signals by means of the neural network, the values of the weighting factors must be quasi-continuously variable. In a training process to determine the wanted values of the weighting factors, the latter are varied, with the aim of minimizing a measure for the deviation between the actual output signals of the network and the desired output signals (nominal responses) for a set of training data, until the actual responses correspond sufficiently precisely to the nominal responses.
For this reason, all known realizations of neural networks are designed either with the aid of analog circuits (P. Muller et al, "A Programmable Analog Neural Computer and Simulator", Adv. Neural Inform. Proc. Systems 1, D. S. Touretzky (ed.), Morgan Kaufmann Publ., San Mateo, Calif., 1989, pp. 712-719) or with the aid of digital circuits with a high word width (N. M. Allinson, "Digital Realization of Self-Organizing Maps", Adv. Neural Inform. Proc. Systems 1, D. S. Touretzky (ed.), Morgan Kaufmann Publ., San Mateo, Calif., 1989, pp. 728-738). In the latter, the continuous input signals and weighting factors are approximated by a large number of discrete stages which are represented by binary variables with a large word width. In all known realizations of ADALINE networks the linear combiners require a very high outlay for circuitry, which hinders the hardware realization of neural networks with comparatively large numbers of neurons.
SUMMARY OF THE INVENTION
Multilayer networks are required for most applications of neural networks in pattern recognition (Rumelhart 1986). The neurons of the first layer are connected here directly to the input nodes. The output signals of the neurons of the first layer form the input signals of the neurons of the second layer. In general the output signals of the neurons of one layer form the input signals of the neurons of the following layer. Since the output signals of all the neurons are binary, the input signals of the neurons of all the higher layers are also automatically binary. The sub-network of the higher layers thus always "sees" binary input signals even if the actual input signals of the overall network can assume values other than only binary ones. The sub-network of the higher layers is thus also termed the "Boolean output layer". The subject-matter of the invention is a process and an arrangement for the realization of ADALINE-type neural networks with Boolean input signals using exclusively Boolean functions and di
REFERENCES:
patent: 4518866 (1985-05-01), Clymer
patent: 4994982 (1991-02-01), Duranton et al.
patent: 5131073 (1992-07-01), Furuta et al.
patent: 5170071 (1992-12-01), Shreve
Mead and Conway, Introduction to VLSI Systems, Addison-Wesley Publ. Col., Reading, Mass., 1980, p. 152.
"Functionality of Multilayer Boolean Neural Networks", R. Al-Alawi et al, Electronics Letters, vol. 25, No. 10, May 11, 1989, pp. 657-659.
"Layered Neural Nets for Pattern Recognition", by B. Wildrow et al, IEEE Transactions on Acoustics, Speech & Signal Processing, vol. 36, No. 7, Jul. 1988, pp. 1109-1118.
"Multi-Scale Dynamic Neural Net Architectures", by L. Atlas et al, IEEE Pacific Rim Conference On Communications, Computers & Signal Processing, Jun. 1, 1989, pp. 509.512.
"A Neural Network with Boolean Output Layer", by P. Strobach, IEEE International Conference on Acoustics, Speech, & Signal Processing, Albuquerque, NM, Apr. 3, 1990, pp. 1-4.
"A Programmable Analog Neural Computer & Simulator", by P. Muller et al, Adv. Neural Inform. Proc. Systems, 1, D. S. Touretzky (ed.), M. Kaufmann Publ., San Mateo, Calif., 1989, pp. 712-719.
"Digital Realisation of Self-Organising Maps", by N. M. Allinson et al, Adv. Neural Inform. Proc. Systems 1, D. S. Touretzky (ed.), M. Kaufmann Publ., San Mateo, Calif., 1989, pp. 728-738.
Hudspeth David R.
Siemens Aktiengesellschaft
LandOfFree
Process and arrangement for the Boolean realization of adaline-t does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process and arrangement for the Boolean realization of adaline-t, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process and arrangement for the Boolean realization of adaline-t will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-216858