Semiconductor memory cell with synthesized load resistors

Details Semiconductor memory cell with synthesized load resistors Semiconductor memory cell with synthesized load resistors

1980-11-24

1982-09-14

Hecker, Stuart N.

Static information storage and retrieval

Systems using particular element

Flip-flop

307279, 365190, G11C 1140

Patent

active

043498949

ABSTRACT:
An MOS memory cell of the static type employs a pair of cross-coupled driver transistors forming a bistable circuit, with load resistors replaced by a pair of series coupling transistors connecting storage nodes to complementary precharged data lines. A two phase clock turns on the coupling transistors in sequence, for refresh, so an intermediate node is charged during a first phase and discharged into the storage nodes during the second phase. Both transistors are turned on at the same time for read or write operations.

REFERENCES:
patent: 3550097 (1970-12-01), Reed
patent: 4103185 (1978-07-01), Denes
patent: 4209851 (1980-06-01), Ponder
patent: 4236229 (1980-11-01), Caudel
Miller, COS/MOS Random Access Memories, IEEE Digest, 3/71, pp. 34-35.

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