Wiring arrangement for semiconductor devices

Details Wiring arrangement for semiconductor devices Wiring arrangement for semiconductor devices

1987-12-29

1989-05-30

James, Andrew J.

357 71, 357 67, H01L 2348, H01L 2354

Patent

active

048355917

ABSTRACT:
A semiconductor integrated circuit with a wiring arrangement for high integration density. The arrangement is dispersed on a semiconductor substrate with a first wiring portion formed on the substrate and a second wiring portion formed on the substrate at a location adjacent to one edge of the first wiring portion. The first wiring portion has a groove or a plurality of indentations formed therein, preferably in the vicinity of the edge thereof that is closer to the second wiring portion, for preventing short-circuiting between the first and second wiring portions through parts of the edge of the first wiring portion which have expanded during a heat treatment.

REFERENCES:
patent: 4525733 (1985-06-01), Losee
patent: 4654692 (1987-03-01), Sukurai et al.
"Elimination of Shorts Between Metallization Lines"--Geldermans--IBM Technical Disclosure Bulletin--vol. 26--No. 5--Oct. 1983--p. 2350.
Spinks, "Introduction to Integrated-Circuit Layout", Prentice-Hall, 1985.
Dingwall et al, "An 8 MHz 8b CMOS Subranging ADC", 1985 IEEE International Solid-State Circuits Conference.

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