Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Patent
1996-12-19
1999-11-02
Grant, William
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
714758, 714761, 714763, 714764, 714767, 714772, 714774, G11C 2900
Patent
active
059789530
ABSTRACT:
A computer system includes a processor bus having processor data and processor check bits for performing error detection and correction of the processor data. A CPU is coupled to the processor bus. A memory sub-system is coupled to the processor bus and includes memory check bits, memory address bits, and memory data bits, and an error detection and correction device for detecting an error in the memory address bits using the memory check bits and for detecting an error in the memory data bits using the memory check bits. The CPU can include a processor from the Pentium.RTM. Pro family of processors. The error detection and correction device generates a syndrome table which includes a plurality of entries mapped to correctable or uncorrectable errors, in which a detected multiple-bit error in the memory data bits is mapped to an uncorrectable error entry and a detected error in the memory address bits is mapped to an uncorrectable error entry. An error detection device is also coupled to the processor bus for detecting an error in the address bits or data bits using the processor check bits.
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Compaq Computer Corporation
Grant William
Marc McDieunel
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