System for speculative branch target prediction having a dynamic

Details System for speculative branch target prediction having a dynamic System for speculative branch target prediction having a dynamic

1997-11-26

1999-11-02

Ellis, Richard L.

Electrical computers and digital processing systems: processing

Processing control

Branching

G06F 932

Patent

active

059789093

ABSTRACT:
A branch prediction unit includes a first branch target buffer, a second branch target buffer, and a static predictor. The first branch target buffer is adapted for storing a first plurality of branch history entries. The second branch target buffer is adapted for storing a second plurality of branch history entries. The static predictor is adapted for determining a static branch prediction for an encountered branch instruction. The second branch target buffer is further adapted to allocate a branch history entry based on the static prediction. A method for predicting program branches in a microprocessor includes fetching a program instruction to be executed by the microprocessor. It is determined if an entry corresponding to the program instruction is stored in a first branch target buffer, and if an entry corresponding to the program instruction is stored in a second branch target buffer. It is determined if the program instruction is a branch instruction. A static prediction is determined for the branch instruction. A branch history entry is allocated in the second branch target buffer based on the static prediction if the first and second branch target buffers do not contain entries corresponding to the program instruction.

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Burch, Carl, PA-8000: A Case Study of Static and Dynamic Branch Prediction, Proceedings of the 1997 IEEE International Conference on Computer Design: VLSI in Computers and Processors, Oct. 12-15, 1997.
Atukorala, Shan, Branch Prediction Methods Used in Modern Superscalar Processors, Proceedings of 1997 International Conference on Information, Communications and Signal Processing, Sep. 9-12, 1997.
Yeh, Tse-Yu, Patt, Yale N., Alternative Implementations of Two-Level Adaptive Branch Prediction, Proceedings of the 19.sup.th Annual International Symposium on Computer Architecture, May 18-21, 1992.
Su, Ching-Long, Despain, Alvin M., Minimizing Branch Misprediction Penalties for Superpipelined Processors, Proceedings of the 27.sup.th Annual International Symposium on Microarchitecture, Nov. 30-Dec. 2, 1994.

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