Delayed update register for an array

Details Delayed update register for an array Delayed update register for an array

1998-10-06

1999-11-02

Eng, David Y.

Electrical computers and digital processing systems: processing

Processing control

Branching

G06F 942

Patent

active

059789077

ABSTRACT:
An update unit for an array in an integrated circuit is provided. The update unit delays the update of the array until a clock cycle in which the functional input to the array is idle. The input port normally used by the functional input is then used to perform the update. During clock cycles between receiving the update and storing the update into the array, the update unit compares the current functional input address to the update address. If the current functional input address matches the update address, then the update value is provided as the output of the array. Otherwise, the information stored in the indexed storage location is provided. In this manner, the update appears to have been performed in the clock cycle that the update value was received, as in a dual-ported array. A particular embodiment of the update unit is a branch prediction array update unit. This unit is described in detail.

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