Electronic digital logic circuitry – Multifunctional or programmable – Having details of setting or programming of interconnections...
Patent
1995-10-23
1997-03-04
Hudspeth, David R.
Electronic digital logic circuitry
Multifunctional or programmable
Having details of setting or programming of interconnections...
326 41, H03K 19177
Patent
active
056083424
ABSTRACT:
A data-cascading hierarchically arranged electrically configurable logic device (ECD) system and an enable-cascading hierarchically arranged ECD system are provided. In both cases, the configuration bitstream includes a local count and at least one remainder count for each ECD. The local count determines the amount of configuration data to be stored locally. By setting this count to zero, an ECD can be bypassed. The remainder count determines the amount of data to be stored by devices down one hierarchical branch from the local ECD. By setting this count to zero, this branch can be bypassed and ECDs of a second branch can be configured sooner. In the data cascading system, the counts determine how data is routed through the ECDs. In the enable cascading system, the data is broadcast to all ECDs. The counts determine when and if the configuration enable inputs of downstream ECDs are to be activated.
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"Product Review 128K Serial EPROM", Motorola Semiconductor Technical Data, Apr., 1994, one page.
Xilinx "The Programmable Logic Data Book", 1994, Xilinix, Inc. 2100 Logic Drive, San Jose, CA 95124, pp. 2-25 to 2-46.
Anderson, Esq. Clifton
Hudspeth David R.
Xilinx , Inc.
Young Edel M.
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