Method of manufacturing Schottky barrier gate FET

Details Method of manufacturing Schottky barrier gate FET Method of manufacturing Schottky barrier gate FET

1991-04-23

1993-02-16

Wilczewski, Mary

Fishing, trapping, and vermin destroying

437 39, 437176, 437177, 437184, 437912, 148DIG140, 257282, H01L 21338, H01L 2128

Patent

active

051871114

ABSTRACT:
The method of manufacturing the SB FET according to the present invention includes a first step of forming a first WN metal film on a GaAs substrate, a second step of forming a first ion-implanted region within the GaAs substrate, by ion implantation of n-type impurities, a third step of forming a second Mo metal film, a fourth step of forming second and third ion-implanted regions adjacent to said first ion-implanted region, within the GaAs substrate, and a fifth step of activating said first, second, and third ion-implanted regions. In the ion implantation of the second step, impurity ions are implanted into the GaAs substrate, through the first metal film. In the fifth step, the first metal film serves as a protective film during the activation of the first, second, and third ion-implanted regions.

REFERENCES:
patent: 4330343 (1982-05-01), Christou et al.
patent: 4546540 (1985-10-01), Ueyanagi et al.
patent: 4581076 (1986-04-01), Badawi
patent: 4601095 (1986-07-01), Kikuchi et al.
patent: 4642879 (1987-02-01), Kawata et al.
patent: 4735913 (1988-04-01), Hayes
patent: 4929567 (1990-05-01), Park et al.
Levy et al., "Self-Aligned Submicron Gate Digital GaAs Integrated Circuits", IEEE Electron Device Letters, vol. EDL-4, No. 4, Apr. 1983, pp. 102-104.
Palmstrom et al., "Metallizations for GaAs Devices and Circuits", in Gallium Arsenide: Materials, Devices, and Circuits, edited by Howes, M. J. and Morgan, D. V., John Wiley and Sons Ltd., (Aug. 29, 1985), pp. 195-261.
Japanese Patent Disclosure (KOKAI) No. 61-42963 filed Aug. 6, 1984; Disclosed Mar. 1, 1986, Inventors: M. Kanamori et al., "Method of Producing Semiconductor Device".
Onodera et al., "A High-Transconductance Self-Aligned GaAs MESFET Fabricated by Through-AIN Implantation," IEEE Transactions on Electron Devices, vol. ED-31, No. 12, pp. 1808-1813, Dec. 1984.
Katsuhara, "Analysis of Implantation Through Insulating Film/GaAs by Boltzmann Transport Equation," Applied Physics Institute, Academic Written Lecture, Spring 1985, 30a-X-s; NEC; Apr. 1985.

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