Method for fabricating a DRAM cell with a T shaped storage capac

Fishing – trapping – and vermin destroying

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437 60, 437919, H01L 2170, H01L 2700

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active

056078749

ABSTRACT:
Two embodiments of a method are described for fabricating a DRAM cell having a T or Y shaped capacitor connected to a MOS transistor with source and drain regions. In a first embodiment, the method comprises using two masks to form a cylindrical hole partial through the insulating layer and a concentric contact hole over the source. A first conductive layer is formed over the first insulating layer, at least completely filling the trench and filling the contact hole. In a key step, the first polysilicon layer is chemically mechanically polished thereby forming a T shaped storage electrode. Next, a capacitor dielectric layer and a top electrode are sequentially formed over at least the T shaped storage electrode. The second embodiment form the contact hole and trench as described above. A conformal first conductive layer is formed over the first insulating layer, filling the contact hole and covering the sidewalls and bottom of the trench, but not filling the trench. A dielectric layer is formed over the first conductive layer at least fills the trench. The dielectric layer and the first conductive layer are chemically mechanically polished forming the Y shaped electrode. Next, a capacitor dielectric layer and a top electrode are formed over the Y shaped storage electrode.

REFERENCES:
patent: 5206183 (1993-04-01), Dennison
patent: 5364809 (1994-11-01), Kwon et al.
patent: 5389568 (1995-02-01), Yun
patent: 5399518 (1995-03-01), Sim et al.
patent: 5429979 (1995-07-01), Lee et al.
patent: 5451539 (1995-09-01), Ryou

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