Wafer scale multi-chip module

Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices

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361709, 361715, 361720, 257707, 257713, 174260, H05K 118, H05K 100

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active

054186870

ABSTRACT:
A wafer scale multi-chip semiconductor module used to interconnect and house a plurality of integrated circuit chips. The wafer scale multi-chip semiconductor module has an interconnect network extending between the integrated circuit chips along the substrate of the semiconductor wafer module, which allows electrical access to the integrated circuit chips by means of electrically conductive bridge connections. The integrated circuit chips are placed in openings in the semiconductor wafer module, allowing for excellent planarity.

REFERENCES:
patent: 4544989 (1985-10-01), Nakabu et al.
patent: 5243498 (1993-09-01), Scofield
patent: 5300812 (1994-04-01), Lupinski et al.
patent: 5313367 (1994-05-01), Ishiyama
M. G. Sage, "Multichip Modules--The Hybrid for Wafer-Scale Integration", Hybrid Circuits, No. 21, Jan. 1990, pp. 36-38.
Cheng Wheling, Mark A. Beiley, and S. Simon Wong, "Membrane Multi-Chip Module Technology on Silicon", IEEE Multi-Chip Module Conference Proceedings, Mar., 1993, Santa Cruz, Calif., pp. 69-73.
Harry F. Lockwood, "Hybrid Wafer Scale Optoelectronic Integration", SPIE vol. 1389--International Conference on Advances in Interconnection and Packaging, 1990, pp. 55-67, (no month provided).
David J. Pedder, "Interconnection Technologies for Multichip Assemblies (ITMA)--A UK Information Technology Engineering Directorate Hybrid Wafer Scale Project", IEEE International Conference on Wafer Scale Integration, San Francisco, Calif., 1993, pp. 95-107, (no month provided).
M. Burnus, H. Taddiken, H.-D. Hartmann, and T. Hillmann-Ruge, "Laserpersonalization of Interconnection Arrays for Hybride ASIC's", IEEE International Conference on Wafer Scale Integration, 1993, San Francisco, Calif., 329-339, (no month provided).
Howard W. Markstein, "Multichip Modules Pursue Wafer Scale Performance", Electronic Packaging & Production, Oct. 1994, pp. 40-45.
Dr. Alastair Trigg, "Silicon Hybrid Multichip Modules", Hybrid Circuit Technology, May 1991, pp. 44-50.
John K. Hagge, "Ultro-Reliable Packaging for Silicon-On-Silicon WSI", IEEE Transactions on Components, Hybrids, and Manufacturing Technology, vol. 12, No. 2, Jun. 1989, pp. 170-179.
Scott Westbrook, "Test Vehicle for MCM-D Interconnect Process Development", IEEE Multi-Chip Module Conference, Santa Cruz, Calif., Mar., 1993, pp. 106-110.
Terry Costlow, "Two Join MCM Market", Electronic Engineering Times, Jun. 7, 1993, p. 58.
Wolfgang Daum, William E. Burdick Jr., and Raymond A. Fillion, "Overlay High-Density Interconnect: A Chips-First Multichip Module Technoloy", IEEE Proceedings, Apr. 1993, pp. 23-29.
Paul D. Franzon and Robert J. Evans, "A Multichip Module Design Process for Notebook Computers", IEEE Proceedings, Apr. 1993, pp. 41-49.
Ron Iscoff, "Are MCMs The New Packaging Champ?", Semiconductor International, Dec. 1992, pp. 48-55.
Bill Blood, "ASIC DESIGN Methodology for Multichip Modules", Hybrid Circuit Technology, Dec. 1991, pp. 20-27.
Gail Lehman-Lamer, Douglas B. Hoy and Kathy M. Middo, "New Multilayer Polyimide Technology Teams with Multilayer Ceramics to Form MultiChip Modules Hybrid Circuit Technology", Oct. 1990, pp. 21-26.
Clive Maxfield and Don Kuk, "A Multichip Module Primer- Does everybody understand MCMs but you?", Printed Circuit Design, Jun. 1992, pp. 17-23.
C. A. Neugebauer, "Comparison of VLSI Packaging Approaches to Wafer Scale Integration", Corporate Research and Development General Electric Co., Schenectady, New York, pp. 462-467, (no date provided).
L. M. Levinson, C. W. Eichelberger, R. J. Wojnarowski, and R. O. Carlson, "High-Density Interconnects Using Laser Lithography", ISHM, 1988 Proceedings, pp. 301-306, (no month provided).
Hyman J. Levinstein, Charles J. Bartlett and Walter J. Bertram, Jr., "Multi-Chip Packaging Technology for VLSI-Based Systems", and Clinton C. Chao, Kenneth D. Scholz, Jacques Leibovitz, Maria Cobarruviaz and Cheng C. Cheng, Multi-Layer Thin-Film Substrates for Multi-Chip Packaging, IEEE Log No. 8927118, Dec. 1988, pp. 472-478.

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