Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Patent
1993-12-27
1995-05-23
Westin, Edward P.
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
327176, 327384, 3652335, H03K 19003
Patent
active
054184797
ABSTRACT:
Noise on address lines is prevented from causing incomplete preparation for reading data after an address transition is detected. One ensures that a flash memory device reads correct data by guaranteeing that each address transition detection, including false address transition detections caused by noise, permits sufficient preparation to read data reliably. An address detected pulse is generated whenever at least one bit of an address changes. If noise causes an invalid address transition detected pulse that is too short to occur, the short pulse will be extended to permit preparation for the memory to be read. Input summation circuitry receives an input pulse and combines the input pulse with a feedback signal to form an input sum signal. Feedback circuitry receives the input sum signal and outputs the feedback signal to the input summation circuitry. The feedback signal holds the input sum signal until the feedback circuit is reset. Delay circuitry receives the input sum signal and, after a predetermined delay, provides as output a delayed signal that prepares the delay circuitry to reset and that also causes the feedback circuitry to reset (i.e., no longer output the feedback signal). Cessation of the input sum signal causes the delay circuitry to reset and halt output of the delay signal. Output summation circuitry receives the input sum signal and combines the input sum signal with the delay signal to form an output sum signal.
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Driscoll Benjamin D.
Intel Corporation
Westin Edward P.
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