Trench dram cell with vertical device and buried word lines

Details Trench dram cell with vertical device and buried word lines Trench dram cell with vertical device and buried word lines

1998-12-03

1999-11-02

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257296, 257301, 257304, 257311, 257618, H01L 2972

Patent

active

059775793

ABSTRACT:
A DRAM array having trench capacitor cells of potentially 4F.sup.2 surface area (F being the photolithographic minimum feature width), and a process for fabricating such an arrays. The array has a cross-point cell layout in which a memory cell is located at the intersection of each bit line and each word line. Each cell in the array has a vertical device such as a transistor, with the source, drain, and channel regions of the transistor being formed from epitaxially grown single crystal silicon. The vertical transistor is formed above the trench capacitor.

REFERENCES:
patent: 5001526 (1991-03-01), Gotou
patent: 5252845 (1993-10-01), Kim et al.
patent: 5334548 (1994-08-01), Shen et al.
patent: 5497017 (1996-03-01), Gonzales
patent: 5504357 (1996-04-01), Kim et al
patent: 5753947 (1998-05-01), Gonzalez
W.F. Richardson et al, "A Trench Transistor Cross-Point Dram Cell ", 1985 IEEE, pp. 714-717, Jan.
Hyun-Jin Cho et al, "A Novel Pillar Dram Cell for 4Gbit And Beyond ", 1998 symposium on VLSI Technology Digest of Technical Papers, pp. 38-39, Jan.
C.J. Radens et al., "A 0.21.mu.m.sup.2 7F.sup.2 Trench Cell with a Locally-Open Globally-Folded Dual Bitline for 1Gb/4Gb Dram ", 1998 Symposium on VLSI Technology Digest of Technical Papers, pp. 36-37. Jan.

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