Pulse generation circuit and memory circuit including same

Details Pulse generation circuit and memory circuit including same Pulse generation circuit and memory circuit including same

1996-02-12

1997-05-06

Dinh, Son T.

Static information storage and retrieval

Addressing

Sync/clocking

36518908, 365194, G11C 800

Patent

active

056277962

ABSTRACT:
A pulse generation circuit of a memory comprises a first logic operation unit for performing a logical operation on an address transition detection pulse and a delayed address transition detection pulse to produce first and second pulses, a switching unit controlled by an externally applied write enable signal for selecting one of the first and second pulses as an output pulse and for inverting the write enable signal, and a second logic operation unit for performing a logical operation on the output pulse and the inverted write enable signal from the switching unit to generate a word line enable signal and a sense amplifying enable signal.

REFERENCES:
patent: 4947379 (1990-08-01), Okuyama
patent: 5258952 (1993-11-01), Coker et al.
patent: 5371716 (1994-12-01), Yamanaka
patent: 5434824 (1995-07-01), Matsuzaki
patent: 5438548 (1995-08-01), Houston

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